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Preliminary User’s Manual U17566EE1V2UM00
Chapter 5 Interrupt Controller (INTC)
This controller is provided with a dedicated Interrupt Controller (INTC) for
interrupt servicing and can process a large amount of maskable and two non-
maskable interrupt requests.
An interrupt is an event that occurs independently of program execution, and
an exception is an event whose occurrence is dependent on program
execution. Generally, an exception takes precedence over an interrupt.
This controller can process interrupt requests from the on-chip peripheral
hardware and external sources. Moreover, exception processing can be
started by the TRAP instruction (software exception) or by generation of an
exception event (i.e. fetching of an illegal opcode) (exception trap).
Eight levels of software-programmable priorities can be specified for each
interrupt request. Starting of interrupt servicing takes no fewer than 5 system
clocks after the generation of an interrupt request.
5.1 Features
• Interrupts
– Non-maskable interrupts: 2 sources
– Maskable interrupts:
– 8 levels of programmable priorities (maskable interrupts)
– Multiple interrupt control according to priority
– Masks can be specified for each maskable interrupt request
– Noise elimination, edge detection and valid edge specification, level
detection for external interrupt request signals
– Wake-up capable
(analogue noise elimination for external interrupt request signals)
– NMI and INTP0 share the same pin
• Exceptions
– Software exceptions: 2 channels with each 16 sources
– Exception traps: 2 sources (illegal opcode exception and debug trap)
Interrupt source
µPD70(F)3420, µPD70(F)3421,
µPD70(F)3422, µPDF3420
µPD70F3424,
µPD70F3425
Internal peripherals
75
82
External
7
8
Software
2
2
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