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Chapter 13
16-bit Multi-Purpose Timer G (TMG)
Preliminary User’s Manual U17566EE1V2UM00
(7)
GCCn1 to GCCn4 - Timer G capture/compare registers with external
PWW-output function
The GCCn1 to GCCn4 registers are 16-bit capture/compare registers of Timer
Gn. They can be assigned to one of the two counters either TMGn0 or TMGn1.
Capture mode
In the capture register mode, these registers capture the value of TMGn0 when
the TBGnm bit (m = 1 to 4) of the TMGCMnH register = 0. When the TBGnm
bit = 1, these registers hold the value of TMGn1.
Compare mode
In compare mode, these registers represent the actual compare value and the
TOGnm-Output (m = 1 to 4) can generate a PWW if they are activated.
Access
In capture mode, these registers can be read in 16-bit units.
In compare mode, these registers can be read/written in 16-bit units.
Address
GCCn1:
<base> + E
H
GCCn2:
<base> + 10
H
GCCn3:
<base> + 12
H
GCCn4:
<base> + 14
H
Initial Value
0000
H
. These registers are cleared by any reset.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GGCn1 to GGCn4 value
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