157
Clock Generator
Chapter 4
Preliminary User’s Manual U17566EE1V2UM00
4.2.4
Control registers for power save modes
The registers described in this section control the begin and end of the power
save modes IDLE, WATCH, Sub-WATCH, and STOP.
Please refer to
“Power save mode activation” on page 179
for instructions and
an example on how to enter a power save mode.
(1)
PSM - Power save mode register
The 8-bit PSM register specifies the power save mode and controls the clock
generation after reset and Sub-WATCH mode release. In addition, it specifies
the source of the Watch Calibration Timer clock WCTCLK.
Access
This register can be read/written in 8-bit or 1-bit units.
Address
FFFF F820
H
.
Initial Value
08
H
. The register is initialized by any reset.
Since the main oscillator is started by the internal firmware are reset, PSM
enters the user’s program with the setting 00
H
.
7
6
5
4
3
2
1
0
0
CMODE
0
0
OSCDIS
0
PSM1
PSM0
R
R/W
R
R
R/W
R
R/W
R/W
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