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Chapter 13
16-bit Multi-Purpose Timer G (TMG)
Preliminary User’s Manual U17566EE1V2UM00
13.2 Function Overview of Each Timer Gn
• 16-bit timer/counter (TMGn0, TMGn1): 2 channels
• Bit length
– Timer Gn registers (TMGn0, TMGn1): 16 bits
• Capture/compare register (GCCny): 6
– 16-bit
– 2 registers are assigned fix to the corresponding one of the 2 counters
– 4 free assignable registers to one of the 2 counters
• Count clock division selectable by prescaler (frequency of peripheral clock:
f
SPCLK0
= 16 MHz)
– In 8 steps from f
SPCLK0
/2 to f
SPCLK0
/256
• Interrupt request sources
– Edge detection circuit with noise elimination.
– Compare-match interrupt requests: 6 types
Perform comparison of capture/compare register with one of the 2
counters (TMGn0, TMGn1) and generate the INTCCGny (y = 0 to 5)
interrupt upon compare match.
– Timer counter overflow interrupt requests: 2 types
In free run mode the INTTMGn0 (INTTMGn1) interrupt is generated when
the count value of TMGn0 (TMGn1) toggles from FFFFH to 0000H.
– In match and clear mode the INTTMGn0 (INTTMGn1) interrupt is
generated when the count value of TMGn0 (TMGn1) matches the GCC0
(GCC1) value.
• PWM output function
– Control of the outputs of TOGn1- through TOGn4-pin in the compare
mode. PWM output can be performed using the compare match timing of
the GCCn1 to GCCn4 register and the corresponding timebase (TMGn0,
TMGn1).
• Output delay operation
– A clock-synchronized output delay can be added to the output signal of
pins TOGn1 to TOGn4.
– This is effective as an EMI counter measure.
• Edge detection and noise elimination filter
– External signals shorter than 1 count clock (f
COUNTn
, not f
SPCLK0
) are
eliminated as noise.
Note
The TIGn1 to TIGn4 and TOGn1 to TOGn4 are each alternative function pins.
The following figure shows the block diagram of Timer Gn.
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