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Chapter 7
Bus and Memory Control (BCU, MEMC)
Preliminary User’s Manual U17566EE1V2UM00
7.5 Configuration of Memory Access
The microcontroller device supports interfacing with various memory devices.
Therefore, the endian format, wait functions and idle state insertions can be
configured.
7.5.1
Endian format
The endian format is specified with the endian configuration register (BEC). It
defines the byte order in which word data is stored.
"Big endian" means that the high-order byte of the word is stored in memory at
the lowest address, and the low-order byte at the highest address. Therefore,
the base address of the word addresses the high-order byte:
Figure 7-8
Big endian addresses within a word
"Little Endian" means that the low-order byte of the word is stored in memory
at the lowest address, and the high-order byte at the highest address.
Therefore, the base address of the word addresses the low-order byte:
Figure 7-9
Little endian addresses within a word
7.5.2
Wait function
Several wait functions are supported:
(1)
Address setup wait
The microcontroller device allows insertion of address setup wait states before
the first access cycle (T1 state). The number of address setup wait states can
be set with the address setup wait control register ASC for each CS area.
Address setup wait states can be inserted when accessing SRAM or page
ROM.
31
24 23
16 15
8
0
7
Byte 0
Byte 1
Byte 2
Byte 3
<base> + 3
<base> + 2
<base> + 1
<base>
access via
addresses
byte position
bit number
31
24 23
16 15
8
0
7
Byte 3
Byte 2
Byte 1
Byte 0
<base> + 3
<base> + 2
<base> + 1
<base>
access via
addresses
byte position
bit number
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