273
Bus and Memory Control (BCU, MEMC)
Chapter 7
Preliminary User’s Manual U17566EE1V2UM00
(3)
ASC - Address setup wait control register
The 16-bit ASC register controls the number of wait states between address
setup and the first access cycle (T1). Each chip select area is controlled
separately. A maximum of three address setup wait states is possible.
Address setup wait states can be inserted when accessing
• SRAM
• page ROM
Access
This register can be read/written in 16-bit units.
Address
FFFF F48A
H
Initial Value
FFFF
H
: After system setup, by default, three address setup wait states are
inserted for each chip select area.
Note
1.
During address setup wait, the external wait function (WAIT pin) is
disabled.
2.
For access to internal memory, the setting of register ASC is neglected. No
wait states are inserted after address setup.
Caution
To initialize an external memory area after a reset, this register has to be set.
Do not access external devices before initialization is finished. Do not change
this register while an external device is accessed.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AC71 AC70 AC61 AC60 AC51 AC50 AC41 AC40 AC31 AC30 AC21 AC20 AC11 AC10 AC01 AC00
CS7
CS6
CS5
CS4
CS3
CS2
CS1
CS0
Table 7-20
ASC register contents
Bit position
Bit name
Function
15 to 0
ACk[1:0]
Sets the number of address setup wait states for each chip select area.
ACk[1:0]
Wait states inserted after address setup
00
B
No wait state inserted
01
B
1 wait state
10
B
2 wait states
11
B
3 wait states
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