538
Chapter 16
Asynchronous Serial Interface (UARTA)
Preliminary User’s Manual U17566EE1V2UM00
Figure 16-12
Allowable baud rate range during reception
As shown in
Figure 16-12
, the receive data latch timing is determined by the
counter set using the UAnCTL2 register following start bit detection. The
transmit data can be normally received if up to the last data (stop bit) can be
received in time for this latch timing.
When this is applied to 11-bit reception, the following is the theoretical result.
FL = (Brate)
-
1
Brate: UARTAn baud rate
k:
Setting value of UAnCTL2.UAnBRS[7:0]
FL:
1-bit data length
Latch timing margin: 2 clocks
Minimum allowable transfer rate:
Therefore, the maximum baud rate that can be received by the destination is
as follows.
Similarly, obtaining the following maximum allowable transfer rate yields the
following.
FL
1 d
a
t
a
fr
a
me (11
×
FL)
FLmin
FLm
a
x
UARTn
tr
a
n
s
fer r
a
te
S
t
a
rt
b
it
Bit 0
Bit 1
Bit 7
P
a
rity
b
it
Minim
u
m
a
llow
ab
le
tr
a
n
s
fer r
a
te
M
a
xim
u
m
a
llow
ab
le
tr
a
n
s
fer r
a
te
S
top
b
it
S
t
a
rt
b
it
Bit 0
Bit 1
Bit 7
P
a
rity
b
it
L
a
tch timing
S
top
b
it
S
t
a
rt
b
it
Bit 0
Bit 1
Bit 7
P
a
rity
b
it
S
top
b
it
FL
min
11
FL
×
k 2
–
2
k
------------
FL
×
–
21k
2
+
2k
-------------------
FL
×
=
=
BRmax
FLmin
11
⁄
(
)
1
–
22k
21k
2
+
-------------------
Brate
×
=
=
10
11
------
FLmax
×
11
FL
×
k
2
+
2
k
------------
FL
×
–
21k
2
–
2k
-------------------
FL
×
=
=
FLmax
21k
2
–
20k
-------------------
FL
11
×
×
=
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