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Preliminary User’s Manual U17566EE1V2UM00
Chapter 16 Asynchronous Serial Interface (UARTA)
The V850E/Dx3 microcontrollers have following instances of the universal
Asynchronous Serial Interface UARTA:
Throughout this chapter, the individual instances of UARTA are identified by
“n”, for example, UARTAn, or UAnCTL0 for the UARTAn control register 0.
16.1 Features
• Transfer rate: 300 bps to 1000 kbps (using dedicated baud rate generator)
• Full-duplex communication:
– Internal UARTA receive data register n (UAnRX)
– Internal UARTA transmit data register n (UAnTX)
• 2-pin configuration:
– TXDAn: Transmit data output pin
– RXDAn: Receive data input pin
• Reception error output function
– Parity error
– Framing error
– Overrun error
• Interrupt sources: 3
– Reception complete interrupt (INTUAnR):
This interrupt occurs upon transfer of receive data from the shift register
to receive buffer register n after serial transfer completion, in the reception
enabled status.
– Transmission enable interrupt (INTUAnT):
This interrupt occurs upon transfer of transmit data from the transmit
buffer register to the shift register in the transmission enabled status.
– Receive error interrupt (INTUAnRE):
This interrupt occurs upon transfer of erroneous receive data.
• Character length: 7, 8 bits
• Parity function: Odd, even, 0, none
• Transmission stop bit: 1, 2 bits
• On-chip dedicated baud rate generator
• MSB-/LSB-first transfer selectable
• Transmit/receive data inverted input/output possible
UARTA
All devices
Instances
2
Names
UARTA0 to UARTA1
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