584
Chapter 18
I
2
C Bus (IIC)
Preliminary User’s Manual U17566EE1V2UM00
Note
The TRCn bit is cleared and SDAn line becomes high impedance when the
WRELn bit is set and the wait state is canceled at the ninth clock by
TRCn = 1.
COIn
Matching address detection
0
Addresses do not match.
1
Addresses match.
Condition for clearing (COIn = 0)
Condition for setting (COIn = 1)
•
When a start condition is detected
•
When a stop condition is detected
•
Cleared by LRELn bit = 1 (communication save)
•
When the IICEn bit changes from 1 to (operation
stop)
•
After reset
•
When the received address matches the local
address (SVAn register) (set at the rising edge of
the eighth clock).
TRCn
Transmit/receive status detection
0
Receive status (other than transmit status). The SDAn line is set to high impedance.
1
Transmit status. The value in the SO latch is enabled for output to the SDAn line (valid starting at
the falling edge of the first byte’s ninth clock).
Condition for clearing (TRCn = 0)
Condition for setting (TRCn = 1)
•
When a stop condition is detected
•
Cleared by LRELn = 1 (communication save)
•
When the IICEn bit changes from 1 to 0 (operation
stop)
•
Cleared by WRELn = 1
Note
•
When the ALDn bit changes from 0 to 1 (arbitration
loss)
•
After reset
Master
• When “1” is output to the first byte’s LSB
(transfer direction specification bit)
Slave
•
When a start condition is detected
When not used for communication
Master
• When a start condition is generated
Slave
• When “1” is input by the first byte’s LSB
(transfer direction specification bit)
ACKDn
ACK detection
0
ACK was not detected.
1
ACK was detected.
Condition for clearing (ACKDn = 0)
Condition for setting (ACKD = 1)
•
When a stop condition is detected
•
At the rising edge of the next byte’s first clock
•
Cleared by LRELn = 1 (communication save)
•
When the IICEn bit changes from 1 to 0 (operation
stop)
•
After reset
•
After the SDAn bit is set to low level at the rising
edge of the SCLn pin’s ninth clock
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