274
Chapter 7
Bus and Memory Control (BCU, MEMC)
Preliminary User’s Manual U17566EE1V2UM00
(4)
DWCn - Data wait control registers
The 16-bit DWCn registers control the number of wait states after the first
access cycle (T1). Each chip select area is controlled separately. A maximum
of seven data wait states is possible.
Access
This register can be read/written in 16-bit units.
Address
DWC0: FFFF F484
H
DWC1: FFFF FFE0
H
Initial Value
7777
H
: After system setup, by default, seven data wait states are inserted for
each chip select area.
Note
1.
For access to internal memory, programmable waits are
not
carried out.
2.
During page ROM on-page access, wait control is performed according to
PRC register setting.
Caution
To initialize an external memory area after a reset, this register has to be set.
Do not access external devices before initialization is finished. Do not change
this register while an external device is accessed.
DWC0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
DW32 DW31 DW30
0
DW22 DW21 DW20
0
DW12 DW11 DW10
0
DW02 DW01 DW00
CS3
CS2
CS1
CS0
DWC1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
DW72 DW71 DW70
0
DW62 DW61 DW60
0
DW52 DW51 DW50
0
DW42 DW41 DW40
CS7
CS6
CS5
CS4
Table 7-21
DWCn registers contents
Bit position
Bit name
Function
15 to 0
DWk[2:0]
Sets the number of wait states after the first access cycle (T1) for each chip
select area.
DWk[2:0]
Number of inserted wait states
000
B
No wait state inserted
001
B
1 wait state
010
B
2 wait states
011
B
3 wait states
...
...
111
B
7 wait states
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