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Chapter 7
Bus and Memory Control (BCU, MEMC)
Preliminary User’s Manual U17566EE1V2UM00
7.5.3
Idle state insertion
To facilitate interfacing with low-speed memory devices, an idle state (TI) can
be inserted between two bus cycles, that means after the T2 state. Idle states
are inserted to meet the data output float delay time on memory read access
for each CS space.
Idle states are used to guarantee the interval until the external data bus is
released by memory. The next bus cycle is started after the idle state(s).
Idle states can be inserted after T2 state when accessing SRAM, external I/O,
external ROM, or page ROM.
The number of idle states can be specified by program using the bus cycle
control register (BCC).
7.6 External Devices Interface Timing
This section presents examples of write and read operations. The states are
abbreviated as:
• T1 and T2 states: Basic states for access.
• TW state: Wait state that is inserted according to the DWC0 and DWC1
register settings and according to the WAIT input.
• TASW state: Address setting wait state that is inserted according to the
ASC register settings.
• TI state: Idle state that is inserted according to the BCC register settings.
Note
For access to page ROM, see
“Page ROM Access Timing” on page 291
.
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