804
Chapter 21
Stepper Motor Controller/Driver (Stepper-C/D)
Preliminary User’s Manual U17566EE1V2UM00
Instruction
When writing data to compare registers, proceed as follows:
1. Confirm
that
MCMPCnk.TEN = 0.
2. Write 8-bit PWM data to MCMPnk0 and MCMPnk1.
3. Set MCMPCnk.ADB0 and MCMPCnk.ADB1 as desired.
4. Set MCMPCnk.TEN = 1 to start the counting operation.
The data in MCMPnk0/MCMPnk1 will automatically be copied to the
compare slave register when the counter overflows. The new pulse width is
valid immediately.
Bit MCMPCnk.TEN is automatically cleared to 0 by hardware.
(3)
Duty Factor
The minimum pulse width that can be generated is zero (output signal is low)
and the maximum pulse width is 255 clock cycles (maximum value of 8-bit
compare registers).
The count range of the timer counter defines the duty factor. It can be set by bit
MCNTCnm.FULL:
• count range 01
H
to FF
H
(MCNTCnm.FULL = 0)
Formula for the duty cycle:
PWM duty = MCMPki / 255
with k = 1 to 6 and i = 0, 1
One count cycle is comprised of 255 clock cycles. A PWM signal with
maximum pulse length is a steady high level signal. The duty factor is 100%.
• count range 00
H
to FF
H
(MCNTCnm.FULL = 1)
Formula for the duty cycle:
PWM duty = MCMPki / 256
with k = 1 to 6 and i = 0, 1
One count cycle is comprised of 256 clock cycles. A PWM signal with
maximum pulse length is comprised of 255 clock cycles at high level and
one clock cycle at low level. The duty factor is 255/256 *100% = 99.6%.
(4)
Advanced precision by 1-bit addition
The precision of the angle of a needle is implicitly defined by the number of bits
of the compare registers MCMPnk0 and MCMPnk1 (8 bit).
If the 1-bit addition circuit is enabled, every second pulse of the PWM signal is
extended by one bit (one clock cycle). In average, a pulse width precision of
1/2 bit (1/2 clock) can be achieved.
The following figures show the timing of PWM output signals with 1-bit addition
disabled and enabled. (See
“Advanced precision by 1-bit addition“ on
page 804
)
Note
1.
The PWM pulse is not generated until the first overflow occurs after the
counting operation has been started.
2.
The PWM signal is two cycle counts delayed compared to the overflow
signal and the match signal. This is not depicted in the figures.
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