363
16-bit Timer/Event Counter P (TMP)
Chapter 11
Preliminary User’s Manual U17566EE1V2UM00
(c) Notes on rewriting TPnCCR0 register
To change the value of the TPnCCR0 register to a smaller value, stop
counting once and then change the set value.
If the value of the TPnCCR0 register is rewritten to a smaller value during
counting, the 16-bit counter may overflow.
Note
1.
Interval time (1): (D
1
+ 1)
×
Count clock cycle
2.
Interval time (NG): ( D
2
+ 1)
×
Count clock cycle
3.
Interval time (2): (D
2
+ 1)
×
Count clock cycle
If the value of the TPnCCR0 register is changed from D
1
to D
2
while the
count value is greater than D
2
but less than D
1
, the count value is
transferred to the CCR0 buffer register as soon as the TPnCCR0 register
has been rewritten. Consequently, the value of the 16-bit counter that is
compared is D
2
.
Because the count value has already exceeded D
2
, however, the 16-bit
counter counts up to FFFFH, overflows, and then counts up again from
0000H. When the count value matches D
2
, the INTTPnCC0 signal is
generated and the output of the TOPn0 pin is inverted.
Therefore, the INTTPnCC0 signal may not be generated at the interval
time “(D
1
+ 1)
×
Count clock cycle” or “(D
2
+ 1)
×
Count clock cycle”
originally expected, but may be generated at an interval of
“( D
2
+ 1)
×
Count clock period”.
FFFFH
16-
b
it co
u
nter
0000H
TPnCE
b
it
TPnCCR0 regi
s
ter
TPnOL0
b
it
TOPn0 pin o
u
tp
u
t
INTTPnCC0
s
ign
a
l
D
1
D
2
D
1
D
1
D
2
D
2
D
2
L
Interv
a
l time (1)
Interv
a
l time (NG)
Interv
a
l
time (2)
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