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LCD Controller/Driver (LCD-C/D)
Chapter 22
Preliminary User’s Manual U17566EE1V2UM00
(1)
LCDC0 - LCD clock control register
The 8-bit LCDC0 register determines the duty cycle frequency f
LCD1
.
Access
This register can be read/written in 8-bit or 1-bit units.
Address
FFFF FB00
H
Initial Value
00
H
. This register is cleared by any reset.
Caution
1.
Bit 4 must always be 0.
2.
Changing the root clock source for LCDLCK will also change the Watch
Timer clock WTCLK. For details refer to the
“Clock Generator“ on page 129
.
Note
The frequency of LCDCLK is determined in the Clock Generator.
The root clock for LCDCLK can be selected from the main, sub, or ring
oscillator. It can be identical with the clock source or it can be a fraction thereof.
7
6
5
4
3
2
1
0
0
0
0
0
LCDC03
LCDC02
LCDC01
LCDC00
R
R
R
R/W
R/W
R/W
R/W
R/W
Table 22-4
LCDC0 register contents
Bit Position
Bit Name
Function
3 to 2
LCDC0[3:2]
Selects the LCD clock
LCDC03
LCDC02
Selected LCD clock (f
LCD0
)
0
0
LCDCLK
0
1
SPCLK7
1
0
SPCLK9
1
1
reserved
1 to 0
LCDC0[1:0]
Selects the duty cycle frequency
LCDC01
LCDC00
Selected duty cycle frequency (f
LCD1
)
0
0
LCD clock divided by 2
6
0
1
LCD clock divided by 2
7
1
0
LCD clock divided by 2
8
1
1
LCD clock divided by 2
9
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