621
I
2
C Bus (IIC)
Chapter 18
Preliminary User’s Manual U17566EE1V2UM00
18.11 Extension Code
• When the higher 4 bits of the receive address are either 0000 or 1111, the
extension code flag (IICSn.EXCn bit) is set for extension code reception and
an interrupt request signal (INTIICn) is issued at the falling edge of the
eighth clock.
The local address stored in the SVAn register is not affected.
• If 11110xx0 is set to the SVAn register by a 10-bit address transfer and
11110xx0 is transferred from the master device, the results are as follows.
Note that the INTIICn signal occurs at the falling edge of the eighth clock
– Higher four bits of data match: EXCn bit = 1
– Seven bits of data match:
IICSn.COIn bit = 1
• Since the processing after the interrupt request signal occurs differs
according to the data that follows the extension code, such processing is
performed by software.
For example, when operation as a slave is not desired after the extension
code is received, set the IICCn.LRELn bit to 1 and the CPU will enter the
next communication wait state.
Table 18-5
Extension code bit definitions
Slave Address
R/W Bit
Description
0000 000
0
General call address
0000 000
1
Start byte
0000 001
X
CBUS address
0000 010
X
Address that is reserved for different bus format
1111 0xx
X
10-bit slave address specification
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