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Chapter 8
DMA Controller (DMAC)
Preliminary User’s Manual U17566EE1V2UM00
8.2 Peripheral and CPU Clock Settings
In order to ensure safe capture of DMA trigger signals from the involved
peripheral functions, a certain minimum relation between the operation clock of
the concerned peripheral function and the CPU system has to be regarded.
In the following table the minimum CPU system clock frequency f
VBCLK
is given
for all peripheral functions operation clocks.
Table 8-1
Peripheral functions and CPU system clocks for DMA transfers (1/2)
Peripheral
Clock controller settings
SPCLKn, PCLKn
configuration
Input clock
[MHz]
Minimum
f
VBCLK
[MHz]
Peripheral clock
Source
ADC
SCC = 00
H
SPCLK0
MainOsc
4
6.00
SCC = 01
H
SPCLK0
PLL/2
16
24.00
SCC = 03
H
SCPS.SPSPS[2:0] = 001
B
SSCG: 32 MHz
SPCLK0
f
SSCGPS
16
24.00
SCC = 03
H
SCPS.SPSPS[2:0] = 011
B
SSCG: 48 MHz
SPCLK0
f
SSCGPS
12
18.00
UARTA
CKC.PERIC = 0
PCLK1
MainOsc
4
6.00
CKC.PERIC = 1
PLL/4
8
12.00
PCLK2
MainOsc
4
6.00
PCLK3
MainOsc/2
2
3.00
PCLK4
MainOsc/4
1
1.5
PCLK5
MainOsc/8
0.5
0.75
PCLK6
MainOsc/16
0.25
0.38
PCLK7
MainOsc/32
0.125
0.19
PCLK8
MainOsc/64
0.0625
0.09
CSIB
CKC.PERIC = 0
PCLK1
MainOsc
4
6.00
CKC.PERIC = 1
PLL/4
8
12.00
PCLK2
MainOsc
4
6.00
PCLK3
MainOsc/2
2
3.00
PCLK4
MainOsc/4
1
1.50
PCLK5
MainOsc/8
0.5
0.75
PCLK6
MainOsc/16
0.250
0.38
SCC = 00
H
SPCLK1
via Baud Rate
Generator
MainOsc
max. 4
min. 0.002
6.00
0.003
SCC = 01
H
PLL/4
max. 8
min. 0.002
12.00
0.003
SCC = 03
H
SCPS.SPSPS[2:0] = 001
B
SSCG: 32 MHz
f
SSCGPS
/2
max. 8
min. 0.002
12.00
0.003
SCC = 03
H
SCPS.SPSPS[2:0] = 011
B
SSCG: 48 MHz
f
SSCGPS
/2
max. 8
min. 0.002
12.00
0.003
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