589
I
2
C Bus (IIC)
Chapter 18
Preliminary User’s Manual U17566EE1V2UM00
(5)
IICXn - IICn function expansion registers
The IICXn registers provide additional transfer data rate configuration in fast-
speed mode. Setting of the IICXn.CLXn is performed in combination with the
IICCLn.SMCn, IICCLn.CLn[1:0], OCKSn.OCKSTHn and OCKSn.OCKSn[1:0]
(refer to
“Transfer rate setting“ on page 590
)
Access
This register can be read/written in 8-bit or 1-bit units.
Address
<base> + 5
H
Initial Value
00
H
. This register is cleared by any reset.
(6)
OCKSn - IICn division clock select registers
The OCKSn registers control the I
2
Cn division clock.
Access
This register can be read/written in 8-bit or 1-bit units.
Address
<base> + 20
H
Initial Value
00
H
. This register is cleared by any reset.
Caution
Bit of OCKSn must be set to “1” after reset and must not be changed
afterwards.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
CLXn
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
0
0
0
1
OCKSTHn
0
OCKSn1
OCKSn0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
OCKSTHn
OCKSn1
OCKSn0
Output clock IICLKPS
0
0
0
IICLK/2
(Only allowed if 4MHz IICLK is used!)
0
0
1
IICLK/3
0
1
0
IICLK/4
0
1
1
IICLK/5
1
0
0
IICLK
(Only allowed if 4MHz IICLK is used!)
Other than above
Setting prohibited
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