349
16-bit Timer/Event Counter P (TMP)
Chapter 11
Preliminary User’s Manual U17566EE1V2UM00
3.
Set the TPnEEE and TPnMD2 to TPnMD0 bits when the TPnCTL0.TPnCE
bit = 0. (The same value can be written when the TPnCE bit = 1.) The
operation is not guaranteed when rewriting is performed with the TPnCE
bit = 1. If rewriting was mistakenly performed, clear the TPnCE bit to 0 and
then set the bits again.
4.
Be sure to clear bits 3, 4, and 7 to 0.
(3)
TPnIOC0 - TMPn I/O control register 0
The TPnIOC0 register is an 8-bit register that controls the timer output
(TOPn0, TOPn1 pins).
Access
This register can be read/written in 8-bit or 1-bit units.
Address
<base> + 2
H
Initial Value
00
H
. This register is initialized by any reset.
Caution
1.
Rewrite the TPnOL1, TPnOE1, TPnOL0, and TPnOE0 bits when the
TPnCTL0.TPnCE bit = 0. (The same value can be written when the TPnCE
bit = 1.) If rewriting was mistakenly performed, clear the TPnCE bit to 0 and
then set the bits again.
2.
Even if the TPnOLm bit is manipulated when the TPnCE and TPnOEm bits
are 0, the TOPnm pin output level varies (m = 0, 1).
7
6
5
4
3
2
1
0
0
0
0
0
TPnOL1
TPnOE1
TPnOL0
TPnOE0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 11-5
TPnIOC0 register contents
Bit position
Bit name
Function
3
TPnOL1
TOPn1 pin output level setting:
0: TOPn1 pin output inversion disabled
1: TOPn1 pin output inversion enabled
2
TPnOE1
TOPn1 pin output setting:
0: Timer output disable
– when TPnOL1 = 0: low level is output from TOPn1 pin
– when TPnOL1 = 1: high level is output from TOPn1 pin
1: Timer output enable
(A square wave is output from TOPn1 pin.)
1
TPnOL0
TOPn0 pin output level setting:
0: TOPn0 pin output inversion disabled
1: TOPn0 pin output inversion enabled
0
TPnOE0
TOPn0 pin output setting:
0: Timer output disable
– when TPnOL0 = 0: low level is output from TOPn0 pin
– when TPnOL0 = 1: high level is output from TOPn0 pin
1: Timer output enable
(A square wave is output from TOPn0 pin.)
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