NEC V850E/Dx3, Preliminary User'S Manual

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DMA Controller (DMAC) Chapter 8
Preliminary User’s Manual U17566EE1V2UM00
8.3.7 DTFRn - DMA trigger source select register
The 8-bit DMA trigger source selection registers are used to control the DMA
transfer triggers for the individual DMA channels. These triggers initiate DMA
transfer requests received from built-in peripheral hardware.
Interrupt signals are used as DMA transfer requests.
These registers support read/write in 8-bit units or bit-wise.
Addresses DTFR0: FFFF FE00H
DTFR1: FFFF FE02H
DTFR2: FFFF FE04H
DTFR3: FFFF FE06H
Note DRQn and DOFLn are set by hardware.
DRQn and DOFLn can be
reset by software. Setting these bits by software is
not possible. A “0” must be written to the respective bit location to reset these
bits.
The bits DTFRn.IFCn[2:0] select the interrupts to be used as DMA trigger
sources according to the following table
:
Caution If the DMA trigger source is changed by modifying DTFRn.IFCn[2:0] bits while
DMA channel n is active, a DMA request may be set accidentally.
Proceed in any of the two ways when changing the DMA trigger source:
1. Disable the DMA channel n by DCHCn.ENn = 0 before changing the DMA
trigger source DTFRn.IFCn[2:0].
7 6 5 4 3 2 1 0
DTFRn DRQn DOFLn DMACTn 0
a
a)
The default value “0” of this bit must not be changed!
0
a
IFCn2 IFCn1 IFCn0
Reset value 0 0 0 0 0 0 0 0
R/W R/W
Note
R/W
Note
R/W R/W R/W R/W R/W R/W
n 0 1 2 3
IFCn2 IFCn1 IFCn0 Channel 0 Channel 1 Channel 2 Channel 3
0 0 0 INTCB1R INTCB2R
a
a)
µPD70F3425, µPD70F3424 only
INTCB1R INTCB2R
a
0 0 1 INTCB1T INTCB2T
a
INTCB1T INTCB2T
a
0 1 0 INTCB0R INTCB0T INTCB0R INTCB0T
0 1 1 INTUA0R INTUA0R INTUA0T INTUA0T
1 0 0 INTUA1R INTUA1R INTUA1T INTUA1T
1 0 1 INTTZ0UV INTTZ0UV INTTZ1UV INTTZ2UV
1 1 0 INTIIC0 INTLCD
a
INTIIC1 INTLCD
a
1 1 1 INTTP0CC1 INTTP1CC1 INTTG0CC1 INTAD
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