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Chapter 28
On-Chip Debug Unit
Preliminary User’s Manual U17566EE1V2UM00
28.2 Controlling the N-Wire Interface
The N-Wire interface pins DRST, DDI, DDO, DCK, DMS are shared with port
functions, see Table 28-2. During debugging the respective device pins are
forced into the N-Wire interface mode and port functions are not available.
Note that N-Wire debugging must be generally permitted by the security bit in
the ID code region (*0x0000 0079[bit7] = 1) of the flash memory.
An internal pull-down resistor - detachable by software - is provided at the
DRST pin to keep the N-Wire interface in reset, if no debugger is connected.
(1)
OCDM - On-chip debug mode register
The OCDM0 control bit in the OCDM register determines the function of these
device pins.
The register can be read or written in 8-bit and 1-bit units.
Address
FFFF F9FC
H
The reset value of OCDM.OCDM0 depends on the reset source.
(2)
Power-On-Clear RESPOC
RESPOC (Power-On-Clear) reset sets OCDM.OCDM0 = 0, i.e. the pins are
defined as port pins. The debugger can not communicate with the controller
and the N-Wire debug circuit is disabled. The first CPU instructions after
RESPOC can not be controlled by the debugger. The application software
must set OCDM.OCDM0 = 1 in order to enable the N-Wire interface and allow
debugger access to the on-chip debug unit.
During and after POC reset (OCDM.OCDM0 = 0) pins P05, P52…P55 are
configured as input ports.
Table 28-2
N-Wire interface pins
GPIO
N-Wire function
Pin
Direction
Description
P05
DRST
Input
N-Wire RCU reset
P52
DDI
Input
N-Wire debug data in
P53
DDO
Output
N-Wire debug data out
P54
DCK
Input
N-Wire interface clock
P55
DMS
Input
N-Wire mode
7
6
5
4
3
2
1
0
Bit name
0
0
0
0
0
0
0
OCDM0
Reset value
0
0
0
0
0
0
0
0/1
a
a)
Reset value depends on reset source (see below)
OCDM0
Usage of N-Wire pins
0
Pins used as port/alternative function pins
1
Pins used as N-Wire interface pins
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