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Chapter 4
Clock Generator
Preliminary User’s Manual U17566EE1V2UM00
4.2.1
General clock generator registers
The general Clock Generator registers control and reflect the operation of the
Clock Generator.
(1)
CKC - Clock Generator control register
The 8-bit CKC register controls the clock management.
Access
This register can be read/written in 8-bit units.
Writing to this register is protected by a special sequence of instructions.
Please refer to
“PHCMD - Command protection register” on page 140
for
details.
Address
FFFF F822
H
.
Initial Value
00
H
. The register is initialized by any reset.
7
6
5
4
3
2
1
0
PLLEN SCEN
DEN
0
PERIC
0
0
0
R/W
R/W
R/W
R
a
a)
These bits may be written, but write is ignored.
R/W
R
a
R
a
R
a
Table 4-4
CKC register contents
Bit position
Bit name
Function
7
PLLEN
a
a)
Before enabling PLLEN or SCEN, make sure that the main oscillator is running and has settled (see also CG-
STAT register). The CPU must operate on the sub, ring or main oscillator clock when setting PLLEN or SCEN
to 1. Before selecting the SSCG / PLL outputs as clock sources for peripherals, ensure by software that the
SSCG / PLL stabilization time has elapsed.The stabilization times are defined in the Electrical Target Specifi-
cation.
PLL enable:
0: PLL disabled.
1: PLL on.
It is not possible to clear this bit by writing to the register. The bit is automatically
cleared in WATCH, Sub-WATCH, or STOP mode.
6
SCEN
a
SSCG enable:
0: SSCG disabled.
1: SSCG on.
It is not possible to clear this bit by writing to the register. The bit is automatically
cleared in WATCH, Sub-WATCH, or STOP mode.
5
DEN
SSCG dithering mode enable:
0: SSCG uses fixed multiplication factor determined by SCFC0, SCFC1
1: SSCG is in dithering mode. The base frequency, determined by the registers
SCFC0, SCFC1, is modulated according to the setup of register SCFMC.
DEN must not be toggled while SCEN is 1.
3
PERIC
Clock source selection for PCLK0/1:
0: Main oscillator is clock source for peripheral clocks PCLK0, PCLK1.
1: PLL (x4) is clock source for peripheral clocks PCLK0, PCLK1.
This bit is automatically cleared in WATCH, Sub-WATCH, or STOP mode.
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