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16-bit Timer/Event Counter P (TMP)
Chapter 11
Preliminary User’s Manual U17566EE1V2UM00
The second (PCLK01) and the third (PCLK02) clock selector input is not
supplied from the clock generator, but derived from the first selector input
PCLK0 inside the timer P.
In case the PLL is disabled the PCLKx clocks are supplied from the main
oscillator, i.e.:
• PCLK0 = 4 MHz
• PCLK01 = PCLK0/2 = 2 MHz
• PCLK02 = PCLK0/4 = 1 MHz
For information about PCLKx, please refer to
“Clock Generator“ on page 129
.
(1)
16-bit counter
This 16-bit counter can count internal clocks or external events.
The count value of this counter can be read by using the TPnCNT register.
When the TPnCTL0.TPnCE bit = 0, the value of the 16-bit counter is FFFFH. If
the TPnCNT register is read at this time, 0000H is read.
Reset input clears the TPnCE bit to 0. Therefore, the 16-bit counter is set to
FFFFH.
(2)
CCR0 buffer register
This is a 16-bit compare register that compares the count value of the 16-bit
counter.
When the TPnCCR0 register is used as a compare register, the value written
to the TPnCCR0 register is transferred to the CCR0 buffer register. When the
count value of the 16-bit counter matches the value of the CCR0 buffer
register, a compare match interrupt request signal (INTTPnCC0) is generated.
The CCR0 buffer register cannot be read or written directly.
The CCR0 buffer register is cleared to 0000H after reset, as the TPnCCR0
register is cleared to 0000H.
(3)
CCR1 buffer register
This is a 16-bit compare register that compares the count value of the 16-bit
counter.
When the TPnCCR1 register is used as a compare register, the value written
to the TPnCCR1 register is transferred to the CCR1 buffer register. When the
count value of the 16-bit counter matches the value of the CCR1 buffer
register, a compare match interrupt request signal (INTTPnCC1) is generated.
The CCR1 buffer register cannot be read or written directly.
The CCR1 buffer register is cleared to 0000H after reset, as the TPnCCR1
register is cleared to 0000H.
(4)
Edge detector
This circuit detects the valid edges input to the TIPn0 and TIPn1 pins. No
edge, rising edge, falling edge, or both the rising and falling edges can be
selected as the valid edge by using the TPnIOC1 and TPnIOC2 registers.
(5)
Output controller
This circuit controls the output of the TOPn0 and TOPn1 pins. The output
controller is controlled by the TPnIOC0 register.
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