NEC V850E/Dx3, Preliminary User'S Manual

Page: 172 / 930

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Chapter 4 Clock Generator
Preliminary User’s Manual U17566EE1V2UM00
(4) Sub-WATCH mode
In Sub-WATCH mode, the clock supply for the CPU and the majority of
peripherals is stopped. Main oscillator, PLL, and SSCG are stopped. By
default, ring oscillator and sub oscillator operation is not influenced. For
exceptions see
“Ring and sub oscillator operation” on page 184 .
The Sub-WATCH mode can be released by
• the unmasked maskable interrupts INTPn, INTCnWUP, INTWTnUV,
INTVCn, INTCBnR
• NMI0, NMIWDT
• RESET, RESPOC, RESWDT, RESCMM, RESCMS
On Sub-WATCH mode release, the CPU starts operation using the following
clocks:
• if PSM.OSCDIS = 1: sub clock source selected before Sub-WATCH mode
was entered, that means, either ring oscillator or sub oscillator (defined by
PCC.SOSCP)
• if PSM.OSCDIS = 0: main oscillator
If the ring oscillator was stopped before entering the Sub-WATCH mode, the
oscillation stabilization time for the ring oscillator is ensured by hardware after
Sub-WATCH release.
PLL and SSCG remain stopped after Sub-WATCH release.
Peripheral clock supply is switched to main oscillator supply, if
PSM.OSCDIS = 0, otherwise the ring oscillator is used for peripheral clocks.
Table 4-27 Clock Generator status in Sub-WATCH mode
Item Status Remarks
Main oscillator unchanged/stopped Stopped if PSM.OSCDIS = 1
Sub oscillator operates
Ring oscillator operates/stopped Stopped if WCC.ROSTP = 1
SSCG stopped
PLL stopped
VBCLK (CPU system) stopped
IICLK stopped
PCLK0, PCLK1 stopped
PCLK2…PCLK15 stopped
SPCLK0, SPCLK1 stopped
SPCLK2…SPCLK15 stopped
FOUTCLK unchanged Stopped, if the selected clock source
stops
WTCLK / LCDCLK unchanged Stopped, if the selected clock source
stops
WDTCLK unchanged/stopped Stopped, if the selected clock source
stops
WCTCLK stopped
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