94
Chapter 2
Pin Functions
Preliminary User’s Manual U17566EE1V2UM00
Filter operation
The input terminal signal is sampled with the sampling frequency f
s
. Spikes
shorter than 2 sampling cycles are suppressed and no internal signal is
generated. Pulses longer than 3 sampling cycles are recognized as valid
pulses and an internal signal is generated. For pulses between 2 and 3
sampling cycles, the behaviour is not defined. The filter operation is illustrated
in
Figure 2-6
.
Figure 2-6
Digital noise removal example
The minimum input terminal pulse width to be validated is defined by the
sampling frequency f
s
. The sampling frequency f
s
is PCLK0.
The digital filter function can be individually enabled for each of the
aforementioned external input signals. The filter is enabled/disabled by the
16-bit registers DFEN0 and DFEN1.
(1)
DFEN0 - Digital filter enable register
The 16-bit DFEN0 register enables/disables the digital filter for TMP0 to TMP3
and TMG0 input channels and for CSIB0 to CSIB2 input channels.
Access
This register can be read/written in 16-bit, 8-bit and 1-bit units.
Address
FFFF F710
H
Initial Value
0000
H
. This register is cleared by any reset.
Input terminal
Filter output
Table 2-53
Digital noise removal features
Sampling frequency
f
s
= PCLK0
Minimum pulse width to
generate an internal signal
16 MHz (PLL enabled)
0.125 – 0.1875 µsec
4 MHz (PLL disabled)
0.5 – 0.75 µsec
15
14
13
12
11
10
9
8
DFENC15 DFENC14 DFENC13 DFENC12 DFENC11 DFENC10 DFENC9 DFENC8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
DFENC7 DFENC6 DFENC5 DFENC4 DFENC3 DFENC2 DFENC1 DFENC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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