277
Bus and Memory Control (BCU, MEMC)
Chapter 7
Preliminary User’s Manual U17566EE1V2UM00
(7)
PRC - Page ROM configuration register
The 16-bit PRC register controls whether a page ROM cycle is on-page or
off-page.
The register specifies the address mask. Masked address bits are not
considered when deciding between on-page or off-page access. Set the mask
according to the number of continuously readable bits.
For page access (cycle is on-page) the register defines the number of inserted
data wait cycles.
Access
This register can be read/written in 16-bit units.
Address
FFFF F49A
H
Initial Value
7000
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
PRW2 PRW1 PRW0
0
0
0
0
0
0
0
0
MA6
MA5
MA4
MA3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 7-24
PRC register contents
Bit position
Bit name
Function
14 to 12
PRW[2:0]
Page ROM on-page wait control.
Sets the number of data waits corresponding to the internal system clock.
PRW[2:0]
Inserted data wait states
000
B
No wait state inserted
001
B
1 wait state
010
B
2 wait states
011
B
3 wait states
...
...
111
B
7 wait states
Note:
The number of wait states defined in the PRC register is only valid if on-page
access is enabled.
If on-page is disabled, the number of wait states is defined by registers DWC0
and DWC1.
3 to 0
MA[6:3]
Mask address.
Setting bits MA6 to MA3 masks the corresponding addresses A6 to A3.
MA6
MA5
MA4
MA3
Number of continuously readable bits
bus width:
8 bits
LBk[1:0]=00
B
bus width:
16 bits
LBk[1:0]=01
B
bus width:
32 bits
LBk[1:0]=10
B
0
0
0
0
8 x 8 bits
4 x 16 bits
2 x 32 bits
0
0
0
1
16 x 8 bits
8 x 16 bits
4 x 32 bits
0
0
1
1
32 x 8 bits
16 x 16 bits
8 x 32 bits
0
1
1
1
64 x 8 bits
32 x 16 bits
16 x 32 bits
1
1
1
1
128 x 8 bits
64 x 16 bits
32 x 32 bits
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