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Preliminary User’s Manual U17566EE1V2UM00
Chapter 3 CPU System Functions
This chapter describes the registers of the CPU, the operation modes, the
address space and the memory areas.
3.1 Overview
The CPU is founded on Harvard architecture and it supports a RISC instruction
set. Basic instructions can be executed in one clock period. Optimized five-
stage pipelining is supported. This improves instruction execution speed.
In order to make the microcontroller ideal for use in digital control applications,
a 32-bit hardware multiplier enables this CPU to support multiply instructions,
saturated multiply instructions, bit operation instructions, etc.
Features summary
The CPU has the following special features:
• Memory space:
– 64 MB linear program space
– 4 GB linear data space
• 32 general purpose registers
• Internal 32-bit architecture
• Five-stage pipeline
• Efficient multiplication and division instructions
• Saturation logic (saturated operation instructions)
• Barrel shifter (32-bit shift in one clock cycle)
• Instruction formats: long and short
• Four types of bit manipulation instructions: set, clear, not, test
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