NEC V850E/Dx3, Preliminary User'S Manual

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Clock Generator Chapter 4
Preliminary User’s Manual U17566EE1V2UM00
Write protection Write protection of this register is achieved in two ways:
• The register can be written only once after Power-On-Clear reset or external
RESET.
• The register is protected by a special sequence via the PHCMD register.
A fail of a write by the special sequence is reflected by PHS.PRERR = 1.
If a write is correctly performed by the special sequence after the register has
already once been written successfully PHS.PRERR remains 0, though the
write has been ignored.
PHS.PRERR shows violations of the special sequence only. It does not reflect
attempts to write the register more than once after reset.
Table 4-13 WCC register contents
Bit position Bit name Function
7 SOSTP Sub oscillator STOP mode control
1: Sub oscillator will stop when STOP mode is entered.
0: Sub oscillator will not stop when STOP mode is entered.
6 to 4 WPS[2:0] WDT clock divider selection:
WPS2 WPS1 WPS0 Clock divider setting
0 0 0
1
0 0 1
1 / 2
0 1 0
1 / 4
0 1 1
1 / 8
1 0 0
1 / 16
1 0 1
1 / 32
1 1 0
1 / 64
1 1 1
1 / 128
3 ROSTP Ring oscillator stop control:
1: Ring oscillator stops if WATCH, Sub-WATCH or STOP mode is entered
0: Ring oscillator always operates
2, 0 SOSCW,
WDTSEL0
Watchdog Timer clock source selection:
SOSCW WDTSEL0 WDT clock source
0 0
Ring oscillator
1 0
Sub oscillator
0 1
Main oscillator
1 1
Setting prohibited
By default, the sub oscillator is disabled in STOP mode (see bit SOSTP). If SOSTP
is 1, choose main or ring oscillator before entering STOP mode.
Caution: Do not specify the sub oscillator, if the sub oscillator is not enabled or
not connected.
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