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Chapter 13
16-bit Multi-Purpose Timer G (TMG)
Preliminary User’s Manual U17566EE1V2UM00
(4)
TMGSTn - Time base status register
The TMGSTn register indicates the status of TMGn0 and TMGn1. For the
CCFGny bit see
“Operation in Free-Run Mode“ on page 451
.
Access
This register can be read/written in 8-bit or 1-bit units.
Address
<base> + 6
H
Initial Value
00
H
. This register is cleared by any reset.
(5)
TMGn0, TMGn1 - Timer Gn 16-bit counter registers
The features of the counters TMGn0 and TMGn1 are listed below:
• Free-running counter that enables counter clearing by compare match of
registers GCCn0/GCCn5
• Counter clear can be set by software.
• Counter stop can be set by software.
Access
These registers can be read/written in 16-bit units.
Address
TMGn0:
<base> + 8
H
TMGn1:
<base> + A
H
Initial Value
0000
H
. This register is cleared by any reset.
7
6
5
4
3
2
1
0
ENFGn1 ENFGn2 CCFGn5 CCFGn4 CCFGn3 CCFGn2 CCFGn1 CCFGn0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 13-7
TMGSTn register contents
Bit position
Bit name
Function
5 to 0
CCFGny
Indicates TMGn0 or TMGn1 overflow status.
0: No overflow
1: Overflow
Caution:
The CCFGny bit is set if a TMGnx overflow has occurred between
two capture input signals. This flag is only updated if the
corresponding GCCny register was read, so first read the GCCny
register and then read this flag if necessary
7 to 6
ENFGnx
Indicates TMGnx operation.
0: indicates operation stopped
1: indicates operation
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TMGn0/TMGn1 value
R/W
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