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Chapter 13
16-bit Multi-Purpose Timer G (TMG)
Preliminary User’s Manual U17566EE1V2UM00
(3)
PWM output (free run)
Basic settings (m = 1 to 4):
Note
The PWM mode is activated by setting the SWFGnm and the CCSGnm bit to
"1".
PWM setting method:
(1)
An usable compare register is one of GCCn1 to GCCn4, and the
corresponding counter must be selected with the TBGnm bit.
(2)
Select a count clock cycle with the CSE12 to CSE10 bits (TMGn1
register) or CSE02 to CSE00 bits (TMGn0 register).
(3)
Specify the active level of a timer output (TOGnm pin) with the ALVGnm
bit.
(4)
When using multiple timer outputs, the user can prevent TOGnm from
becoming active simultaneously by setting the OLDEn bit of TMGMHn
register to provide step-by-step delays for TOGnm. (This capability is
useful for reducing noise and current.)
(5)
Write data to GCCnm.
(6)
Start timer operation by setting POWERn bit and TMGn0E bit (or
TMGn1E bit).
PWM operation:
(1)
When the value of the counter matches the value of GCCnm, a match
interrupt (INTCCGnm) is output.
(2)
When the counter overflows, an overflow interrupt (INTTMGn0 or
INTTMGn1) is generated.
(3)
TOGnm does not make a transition until the first overflow occurs. (Even if
the counter is cleared by software, TOGnm does not make a transition
until the next overflow occurs. After the first overflow occurs, TOGnm is
activated.
(4)
When the value of the counter matches the value of GCCnm, TOGnm is
deactivated, and a match interrupt (INTCCGnm) is output. The counter is
not cleared, but continues count-up operation.
(5)
The counter overflows, and INTTMGn0 or INTTMGn1 is output to activate
TOGnm. The counter resumes count-up operation starting with 0000H.
Bit
Value
Remark
CCSGn0
0
free run mode
CCSGn5
0
SWFGnm
1
Note
enable TOGnm
CCSGnm
1
Note
Compare mode for
GCCnm
TBGnm
X
assign counter
for GCCnm
0: TMGn0
1: TMGn1
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