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Chapter 11
16-bit Timer/Event Counter P (TMP)
Preliminary User’s Manual U17566EE1V2UM00
(6)
TPnOPT0 - TMPn option register 0
The TPnOPT0 register is an 8-bit register used to set the capture/compare
operation and detect an overflow.
Access
This register can be read/written in 8-bit or 1-bit units.
Address
<base> + 5
H
Initial Value
00
H
. This register is initialized by any reset.
Caution
1.
Rewrite the TPnCCS1 and TPnCCS0 bits when the TPnCE bit = 0. (The
same value can be written when the TPnCE bit = 1.) If rewriting was
mistakenly performed, clear the TPnCE bit to 0 and then set the bits again.
2.
Be sure to clear bits 1 to 3, 6, and 7 to 0.
7
6
5
4
3
2
1
0
0
0
TPnCCS1
TPnCCS10
0
0
0
TPnOVF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 11-8
TPnOPT0 register contents
Bit position
Bit name
Function
5
TPnCCS1
TPnCCR1 register capture/compare selection:
0: compare register selected
1: capture register selected
The TPnCCS1 bit setting is valid only in the free-running timer mode.
4
TPnCCS0
TPnCCR0 register capture/compare selection:
0: compare register selected
1: capture register selected
The TPnCCS0 bit setting is valid only in the free-running timer mode.
0
TPnOVF
TMPn overflow detection flag:
Set (1):
Overflow occurred
Reset (0): TPnOVF bit 0 written or TPnCTL0.TPnCE bit = 0
•
The TPnOVF bit is reset when the 16-bit counter count value overflows from
FFFFH to 0000H in the free-running timer mode or the pulse width
measurement mode.
•
An interrupt request signal (INTTPnOV) is generated at the same time that
the TPnOVF bit is set to 1. The INTTPnOV signal is not generated in modes
other than the free-running timer mode and the pulse width measurement
mode.
•
The TPnOVF bit is not cleared even when the TPnOVF bit or the TPnOPT0
register are read when the TPnOVF bit = 1.
•
The TPnOVF bit can be both read and written, but the TPnOVF bit cannot be
set to 1 by software. Writing 1 has no influence on the operation of TMPn.
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