251
Bus and Memory Control (BCU, MEMC)
Chapter 7
Preliminary User’s Manual U17566EE1V2UM00
• VSB: V850 system bus
• VDB: V850 data bus
• VFB: V850 fetch bus
BCU
The Bus Control Unit (BCU) controls the access to on-chip peripherals, to
external memory controller (MEMC), the VSB RAM and VSB Flash of the
µPD70F3426 device.
For access to external devices, the BCU generates the necessary control
signals (chip select signals) for the Memory Controller.
Memory Controller
The 64 MB address range is divided into 2-MB, 4-MB and 8-MB memory
banks. Each of the memory banks can be assigned to an external device via
the chip area select control registers CSC0 and CSC1.
If an instruction uses such an address, a chip select signal is generated. The
device supports four chip select signals (CS0, CS1, CS3 and CS4). Each chip
select signal covers a certain address range, also called “chip select area”. For
details see
“Memory banks and chip select signals” on page 252
.
Additional byte enable signals BE0 to BE3 indicate valid data on any of the four
bytes of the 32-bit data bus D[31:0].
The Memory Controller generates the control signals for access to the external
devices. For example, it generates the read strobe (RD) and the write strobe
(WR). From the 26 bit address of the CPU, the lower 24 bits are passed to the
external device.
If two chip select signals are specified in the CSCn registers for a single
memory bank, the priority control selects one of the chip select signals. The
priority order is given in
“CSCn - Chip area select control registers” on
page 265
.
The external signals of the Memory Controller and their state during and after
reset are listed in the following table:
All pins are in input port mode after reset. Refer to
“Pin Functions” on page 33
.
Table 7-1
Memory Controller external connections and reset states
Signal name
I/O
State
during reset
State
after reset
Function
A[23:0]
O
tbd
O
Address bus
D[31:16]
I/O
Hi-Z (3-state)
Port input
Data bus
D[15:0]
tbd
O
CS0
O
tbd
I
Chip select signal
CS1
CS3
CS4
BE0
O
tbd
O
Byte enable signal
BE1
BE2
O
Hi-Z (3-state)
Port input
BE3
RD
O
tbd
O
Read strobe
WR
O
tbd
O
Write strobe
WAIT
I
tbd
I
Data wait
BCLK
O
Hi-Z (3-state)
Port input
Bus clock
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