392
Chapter 11
16-bit Timer/Event Counter P (TMP)
Preliminary User’s Manual U17566EE1V2UM00
(3)
Operation timing in one-shot pulse output mode
(a) Note on rewriting TPnCCRm register
To change the set value of the TPnCCRm register to a smaller value, stop
counting once, and then change the set value.
If the value of the TPnCCRm register is rewritten to a smaller value during
counting, the 16-bit counter may overflow.
When the TPnCCR0 register is rewritten from D
00
to D
01
and the TPnCCR1
register from D
10
to D
11
where D
00
> D
01
and D
10
> D
11
, if the TPnCCR1
register is rewritten when the count value of the 16-bit counter is greater
than D
11
and less than D
10
and if the TPnCCR0 register is rewritten when
the count value is greater than D
01
and less than D
00
, each set value is
reflected as soon as the register has been rewritten and compared with the
count value. The counter counts up to FFFFH and then counts up again
from 0000H. When the count value matches D
11
, the counter generates the
INTTPnCC1 signal and asserts the TOPn1 pin. When the count value
matches D
01
, the counter generates the INTTPnCC0 signal, deasserts the
TOPn1 pin, and stops counting.
Therefore, the counter may output a pulse with a delay period or active
period different from that of the one-shot pulse that is originally expected.
FFFFH
16-
b
it co
u
nter
0000H
TPnCE
b
it
TPnCCR0 regi
s
ter
INTTPnCC0
s
ign
a
l
TOPn0 pin o
u
tp
u
t
TPnCCR1 regi
s
ter
INTTPnCC1
s
ign
a
l
TOPn1 pin o
u
tp
u
t
Extern
a
l trigger inp
u
t
(TIPn0 pin inp
u
t)
D
10
D
11
D
00
D
01
D
00
D
10
D
10
D
10
D
01
D
11
D
00
D
00
Del
a
y
(D
10
)
Active level width
(D
00
−
D
10
+ 1)
Del
a
y
(D
10
)
Active level width
(D
00
−
D
10
+ 1)
Del
a
y
( D
11
)
Active level width
(D
01
−
D
11
+ 1)
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