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Interrupt Controller (INTC)
Chapter 5
Preliminary User’s Manual U17566EE1V2UM00
The priority order for multiple interrupt processing control has 8 levels, from 0
to 7 for each maskable interrupt request (0 is the highest priority), but it can be
set as desired via software. Setting of the priority order level is done using the
PPRn0 to PPRn2 bits of the interrupt control request register (PlCn), which is
provided for each maskable interrupt request. After system reset, an interrupt
request is masked by the PMKn bit and the priority order is set to level 7 by the
PPRn0 to PPRn2 bits.
The priority order of maskable interrupts is as follows.
(High) Level 0 > Level 1 > Level 2 > Level 3 > Level 4 >
Level 5 > Level 6 > Level 7 (Low)
Interrupt processing that has been suspended as a result of multiple
processing control is resumed after the processing of the higher priority
interrupt has been completed and the RETI instruction has been executed.
A pending interrupt request is acknowledged after the current interrupt
processing has been completed and the RETI instruction has been executed.
Caution
In a non-maskable interrupt processing routine (time until the RETI instruction
is executed), maskable interrupts are suspended and not acknowledged.
5.8 Interrupt Response Time
The following table describes the interrupt response time (from interrupt
generation to start of interrupt processing).
Except in the following cases, the interrupt response time is a minimum of 5
clocks.
• During software or hardware STOP mode
• When an external bus is accessed
• When there are two or more successive interrupt request non-sampling
instructions (see
“Periods in Which Interrupts Are Not Acknowledged“ on
page 228
).
• When the interrupt control register is accessed
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