421
16-bit Timer/Event Counter P (TMP)
Chapter 11
Preliminary User’s Manual U17566EE1V2UM00
Figure 11-38
Basic timing in pulse width measurement mode
When the TPnCE bit is set to 1, the 16-bit counter starts counting. When the
valid edge input to the TIPnm pin is later detected, the count value of the 16-bit
counter is stored in the TPnCCRm register, the 16-bit counter is cleared to
0000H, and a capture interrupt request signal (INTTPnCCm) is generated.
The pulse width is calculated as follows.
First pulse width = (D
0
+ 1)
×
Count clock cycle
Second and subsequent pulse width = (D
N
-
D
N
-
1
)
×
Count clock cycle
If the valid edge is not input to the TIPnm pin even when the 16-bit counter
counted up to FFFFH, an overflow interrupt request signal (INTTPnOV) is
generated at the next count clock, and the counter is cleared to 0000H and
continues counting. At this time, the overflow flag (TPnOPT0.TPnOVF bit) is
also set to 1. Clear the overflow flag to 0 by executing the CLR instruction via
software.
If the overflow flag is set to 1, the pulse width can be calculated as follows.
First pulse width = (D
0
+ 10001H)
×
Count clock cycle
Second pulse width and on = ( D
N
-
D
N
-
1
)
×
Count clock cycle
FFFFH
16-
b
it co
u
nter
0000H
TPnCE
b
it
TIPnm pin inp
u
t
TPnCCRm regi
s
ter
INTTPnCCm
s
ign
a
l
INTTPnOV
s
ign
a
l
TPnOVF
b
it
D
0
0000H
D
1
D
2
D
3
Cle
a
red to 0
b
y
CLR in
s
tr
u
ction
electronic components distributor
