579
I
2
C Bus (IIC)
Chapter 18
Preliminary User’s Manual U17566EE1V2UM00
(1)
IICCn - IICn control registers
The IICCn registers enable/stop I
2
Cn operations, set the wait timing, and set
other I
2
Cn operations.
Access
This register can be read/written in 8-bit or 1-bit units.
Address
<base> + 2
H
Initial Value
00
H
. This register is cleared by any reset.
7
6
5
4
3
2
1
0
IICEn
LRELn
WRELn
SPIEn
WTIMn
ACKEn
STTn
SPTn
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IICEn
Specification of I
2
Cn operation enable/disable
0
Operation stopped. IICSn register reset
Note 1
. Internal operation stopped.
1
Operation enabled.
Condition for clearing (IICEn = 0)
Condition for setting (IICEn = 1)
•
Cleared by instruction
•
After reset
•
Set by instruction
LRELn
Exit from communications
0
Normal operation
1
This exits from the current communication operation and sets stand-by mode. This setting is
automatically cleared after being executed. Its uses include cases in which a locally irrelevant
extension code has been received.
The SCLn and SDAn lines are set to high impedance.
The STTn and SPTn bits and the MSTSn, EXCn, COIn, TRCn, ACKDn, and STDn bits of the IICSn
register are cleared.
The stand-by mode following exit from communications remains in effect until the following communication entry
conditions are met.
•
After a stop condition is detected, restart is in master mode.
•
An address match occurs or an extension code is received after the start condition.
Condition for clearing (LRELn = 0)
Note 2
Condition for setting (LRELn = 1)
•
Automatically cleared after execution
•
After reset
•
Set by instruction
WRELn
Wait cancellation control
0
Wait not cancelled
1
Wait cancelled. This setting is automatically cleared after wait is cancelled.
Condition for clearing (WRELn = 0)
Note 2
Condition for setting (WRELn = 1)
•
Automatically cleared after execution
•
After reset
•
Set by instruction
electronic components distributor
