559
Clocked Serial Interface (CSIB)
Chapter 17
Preliminary User’s Manual U17566EE1V2UM00
Read the CBnRX register.
(8) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to
stop the operation of CSIBn (end of transmission/reception).
To continue transfer, repeat steps (5) to (7) before (8).
Note
In order to start the entire data transfer the CBnTX register has to be written
initially, as done in step (5) above. If this step is omitted also no data will be
received.
Discontinued
transmission
In case the CSIB is operating in continuous slave transmission mode
(CBnCTL0.CBnTMS = 1, CBnCTL1.CBnCKS[2:0] = 111
B
) and new data is not
written to the CBnTX register the SOBn pin outputs the level of the last bit.
Table 17-8
outlines this behaviour.
Table 17-8
Discontinued slave transmission
The example shows the situation that two data bytes (55
H
, AA
H
) are
transmitted correctly, but the third (96
H
) fails.
(1) Data 55
H
is written (by the CPU or DMA) to CBnTX.
(2) The master issues the clock SCKBn and transmission of 55
H
starts.
(3) INTCBnT is generated and the next data AA
H
is written to CBnTX
promptly, i.e. before the first data has been transmitted completely.
(4) Transmission of the second data AA
H
continues correctly and INTCBnT is
generated. But this time the next data is not written to CBnTX in time.
(5) Since there is no new data available in CBnTX, but the master continuous
to apply SCKBn clocks, SOBn remains at the level of the transmitted last
bit.
(6) New data (96
H
) is written to CBnTX.
(7) With the next SCKBn cycle transmission of the new data (96
H
) starts.
As a consequence the master receives a corrupted data byte from (5)
onwards, which is made up of a random number of the repeated last bit of the
former data and some first bits of the new data.
0
S
CKBn
S
OBn
INTCBnT
CBnTX
CBnT
S
F
1
0
1
0
0
1
1
1
0
1
0
1
0
1
0
55H
AAH
1
0
0
1
0
1
1
0
96H
(1)
(2)
(4)
(5)
(6)
(7)
(3)
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