NEC V850E/Dx3, Preliminary User'S Manual

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16-bit Multi-Purpose Timer G (TMG) Chapter 13
Preliminary User’s Manual U17566EE1V2UM00
13.4 TMG Registers
The Timers Gn are controlled and operated by means of the following
registers:
Table 13-2 TMGn registers overview
Register name Shortcut Address
Timer Gn mode register TMGMn <base>
Timer Gn channel mode register TMGCMn <base> + 2
H
Timer Gn output control register OCTLGn <base> + 4
H
Timer Gn time base status register TMGSTn <base> + 6
H
Timer Gn count register 0 TMG00 <base> + 8
H
Timer Gn count register 1 TMG01 <base> + A
H
Timer Gn capture/compare register 0 GCC00 <base> + C
H
Timer Gn capture/compare register 1 GCC01 <base> + E
H
Timer Gn capture/compare register 2 GCC02 <base> + 10
H
Timer Gn capture/compare register 3 GCC03 <base> + 12
H
Timer Gn capture/compare register 4 GCC04 <base> + 14
H
Timer Gn capture/compare register 5 GCC05 <base> + 16
H
Table 13-3 TMGn register base address
Timer Base address
TMG0 FFFF F6A0
H
TMG1 FFFF F6C0
H
TMG2 FFFF F6E0
H
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