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Asynchronous Serial Interface (UARTA)
Chapter 16
Preliminary User’s Manual U17566EE1V2UM00
Caution
1.
Be sure to read the UAnRX register even when a reception error occurs. If
the UAnRX register is not read, an overrun error occurs during reception of
the next data, and reception errors continue occurring indefinitely.
2.
The operation during reception is performed assuming that there is only one
stop bit. A second stop bit is ignored.
3.
When reception is completed, read the UAnRX register after the reception
complete interrupt request signal (INTUAnR) has been generated, and clear
the UAnPWR or UAnRXE bit to 0. If the UAnPWR or UAnRXE bit is cleared
to 0 before the INTUAnR signal is generated, the read value of the UAnRX
register cannot be guaranteed.
4.
If receive completion processing (INTUAnR signal generation) of UARTAn
and the UAnPWR bit = 0 or UAnRXE bit = 0 conflict, the INTUAnR signal
may be generated in spite of these being no data stored in the UAnRX
register.
To complete reception without waiting INTUAnR signal generation, be sure
to clear (0) the interrupt request flag (UAnRIF) of the UAnRIC register, after
setting (1) the interrupt mask flag (UAnRMK) of the interrupt control register
(UAnRIC) and then set (1) the UAnPWR bit = 0 or UAnRXE bit = 0.
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