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Chapter 4
Clock Generator
Preliminary User’s Manual U17566EE1V2UM00
– Watch Timer interrupts INTWTnUV
The Watch Timer clock WTCLK must be active and the Watch Timer must
be enabled.
– Watch Calibration Timer interrupt INTTM01
The Watch Calibration Timer clock WCTCLK must be active and the
Watch Calibration Timer must be enabled.
– Voltage Comparators interrupts INTVCn
The Voltage Comparators must be enabled.
– CSIB receive interrupts INTCBnR
The CSIB must be operated in slave reception mode and the appropriate
ports must be configured correctly.
Note that not all these signals are available in all power save modes.
The following signals can awake the controller from the power save mode
HALT, provided the appropriate ports and modules are correctly configured
and the required clocks are active:
• all reset signals
• the non-maskable interrupts NMI0, NMIWDT
• all maskable interrupts
To grant wake-up capability to maskable interrupts these interrupts have to be
unmasked by setting the dedicated mask flags xxMK to 0 (refer to
“Interrupt
Controller (INTC)” on page 187
).
A general disable of maskable interrupts acknowledgement (“DI”, i.e.
PSW.ID = 1) does not affect their wake-up capability.
After power save
mode
After power save mode release, the clock source for CPU operation should be
checked. If the user application issues a wake-up request immediately after
power save mode request, the power save mode may not be entered and the
clock sources remain as programmed before the stand-by request.
After power save mode release, the same procedure as for system reset is
required to set up the clock supply for the application.
Note
In the following tables the clock status "operates" does not necessarily mean
that the functions that use this clock source are operating as well.
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