153
Clock Generator
Chapter 4
Preliminary User’s Manual U17566EE1V2UM00
Note
Only POC and external RESET can clear the TCC register. Only one write
access to TCC is allowed after reset release. Once the TCC has been written,
it ignores new write accesses until the next POC or external RESET is issued.
Write protection
Write protection of this register is achieved in two ways:
• The register can be written only once after Power-On-Clear reset or external
RESET.
• The register is protected by a special sequence via the PHCMD register.
A fail of a write by the special sequence is reflected by PHS.PRERR = 1.
If a write is correctly performed by the special sequence after the register has
already once been written successfully PHS.PRERR remains 0, though the
write has been ignored.
PHS.PRERR shows violations of the special sequence only. It does not reflect
attempts to write the register more than once after reset.
2, 0
WTSOS,
WTSEL0
Clock source for Watch Timer and LCD controller:
WTSOS
WTSEL0
Clock source
0
0
Ring oscillator
1
0
Sub oscillator
0
1
Main oscillator
1
1
Setting prohibited
By default, the sub oscillator is disabled in STOP mode (see bit WCC.SOSTP). If
WCC.SOSTP is 1, choose main or ring oscillator before entering STOP mode.
Caution:
Do not specify the sub oscillator, if the sub oscillator is not enabled or
not connected.
Table 4-14
TCC register contents (2/2)
Bit position
Bit name
Function
electronic components distributor
