150
Chapter 4
Clock Generator
Preliminary User’s Manual U17566EE1V2UM00
4.2.3
Control registers for peripheral clocks
This section describes the registers used for specifying the sources and
operation modes for the clocks provided for the on-chip peripherals.
These clocks are the clocks for the Watchdog and Watch Timers, the SPCLKn
clocks, FOUTCLK, and IICLK.
Note
Be aware that the WCC register controls not only the generation of the
Watchdog Timer clock. It defines also the run/stop mode of the sub and ring
oscillators when certain power save modes are entered.
(1)
WCC - Watchdog Timer clock control register
The 8-bit WCC register controls the Watchdog Timer clock. This register can
be changed only once after any reset.
Writing to this register is protected by a special sequence of instructions.
Please refer to
“PHCMD - Command protection register” on page 140
for
details.
Access
This register can be read/written in 8-bit units.
Address
FFFF F826
H
.
Initial Value
00
H
. The register is initialized by any reset.
Caution
Bit 1 of WCC must be set to “1” after reset and must not be altered afterwards.
7
6
5
4
3
2
1
0
SOSTP
WPS2
WPS1
WPS0
ROSTP
SOSCW
1
WDTSEL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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