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16-bit Timer/Event Counter P (TMP)
Chapter 11
Preliminary User’s Manual U17566EE1V2UM00
(5)
TPnIOC2 - TMPn I/O control register 2
The TPnIOC2 register is an 8-bit register that controls the valid edge of the
external event count input signal (TIPn0 pin) and external trigger input signal
(TIPn0 pin).
Access
This register can be read/written in 8-bit or 1-bit units.
Address
<base> + 4
H
Initial Value
00
H
. This register is initialized by any reset.
Caution
1.
Rewrite the TPnEES1, TPnEES0, TPnETS1, and TPnETS0 bits when the
TPnCTL0.TPnCE bit = 0. (The same value can be written when the TPnCE
bit = 1.) If rewriting was mistakenly performed, clear the TPnCE bit to 0 and
then set the bits again.
2.
The TPnEES1 and TPnEES0 bits are valid only when the
TPnCTL1.TPnEEE bit = 1 or when the external event count mode
(TPnCTL1.TPnMD2 to TPnCTL1.TPnMD0 bits = 001) has been set.
7
6
5
4
3
2
1
0
0
0
0
0
TPnEES1
TPnEES0
TPnETS1
TPnETS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 11-7
TPnIOC2 register contents
Bit position
Bit name
Function
3 to 2
TPnEES[1:0]
External event count input signal (TIPn0 pin) valid edge setting:
TPnEES1
TPnEES0 External event count valid edge of TIPn0
0
0
No edge detection (external event invalid)
0
1
Detection of rising edge
1
0
Detection of falling edge
1
1
Detection of both edges
1 to 0
TPnETS[1:0]
Capture trigger input signal (TIPn0 pin) valid edge setting:
TPnETS1
TPnETS0 External trigger input valid edge of TIPn0
0
0
No edge detection (external trigger invalid)
0
1
Detection of rising edge
1
0
Detection of falling edge
1
1
Detection of both edges
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