600
Chapter 18
I
2
C Bus (IIC)
Preliminary User’s Manual U17566EE1V2UM00
(2)
When master and slave devices both have a nine-clock wait
(master: transmission, slave: reception, and ACKEn bit = 1)
Figure 18-12
Wait signal (2/2)
A wait may be automatically generated depending on the setting of the
IICCn.WTIMn bit.
Normally, when the IICCn.WRELn bit is set to 1 or when FFH is written to the
IICn register on the receiving side, the wait status is cancelled and the
transmitting side writes data to the IICn register to cancel the wait status.
The master device can also cancel its own wait status via either of the following
methods.
• By setting the IICCn.STTn bit to 1
• By setting the IICCn.SPTn bit to 1
S
CLn
6
S
DAn
7
8
9
1
2
3
S
CLn
IICn
6
H
7
8
1
2
3
D2
D1
D0
ACK
D7
D6
D5
9
IICn
S
CLn
ACKEn
M
as
ter (Tx)
M
as
ter
a
nd
s
l
a
ve
b
oth w
a
it
a
fter o
u
tp
u
t of ninth clock.
IICn d
a
t
a
write (c
a
ncel w
a
it)
S
l
a
ve (Rx)
FFH i
s
written to IICn regi
s
ter
or WRELn
b
it i
s
s
et to 1.
O
u
tp
u
t
a
ccording to previo
us
ly
s
et ACKEn
b
it v
a
l
u
e
Tr
a
n
s
fer line
s
W
a
it
s
ign
a
l
from m
as
ter
/
s
l
a
ve
W
a
it
s
ign
a
l
from
s
l
a
ve
electronic components distributor
