TC1796
Peripheral Units (Vol. 2 of 2)
Synchronous Serial Interface (SSC)
User’s Manual
20-5
V2.0, 2007-07
SSC, V2.1
20.1.2.1 Operating Mode Selection
The operating mode of the serial channel SSC is controlled by its Control Register, CON.
Status information is contained in its Status Register, STAT.
The shift register of the SSC is connected to both the transmit pin and the receive pin via
the pin control logic (see block diagram in
). Transmission and reception of
serial data are synchronized and take place at the same time, that is, the same number
of transmitted bits is also received. Transmit data is written into the Transmit Buffer TB.
It is moved to the shift register as soon as this is empty. An SSC master (CON.MS = 1)
immediately begins transmitting, while an SSC slave (CON.MS = 0) will wait for an active
shift clock. When the transfer starts, the busy flag STAT.BSY is set and the transmit
interrupt request line (TIR) will be activated to indicate that the Transmit Buffer Register
(TB) may be reloaded. When the number of bits (2 to 16, as programmed) have been
transferred, the contents of the shift register are moved to the Receive Buffer Register
(RB), and the receive interrupt request line (RIR) will be activated. If no further transfer
is to take place (TB is empty), STAT.BSY will be cleared at the same time. Software
should not modify STAT.BSY, as this flag is hardware-controlled.
Note: Only one SSC can be master at a given time.
The following features of the serial data bit transfer can be programmed:
•
The data width can be selected from 2 bits to 16 bits
•
A transfer may start with the LSB or the MSB
•
The shift clock may be idle low or idle high
•
The data bits may be shifted with the leading or trailing edge of the clock signal
•
The baud rate (shift clock) can be set from 572.2 bit/s up to 37.5 Mbit/s
(@ 75 MHz module clock)
•
The shift clock can be generated (master) or received (slave)
These features allow the SSC to be adapted to a wide range of applications that require
serial data transfer.
The Data Width Selection
supports the transfer of frames of any data length from 2-bit
“characters” up to 16-bit “characters”. Starting with the LSB (CON.HB = 0) allows
communication with such devices as an SSC device in Synchronous Mode, or 8051-like
serial interfaces. Starting with the MSB (CON.HB = 1) allows operation compatible with
the SPI interface.
Regardless of the data width selected and whether the MSB or the LSB is transmitted
first, the transfer data is always right-aligned in registers TB and RB, with the LSB of the
transfer data in bit 0 of these registers. The data bits are rearranged for transfer by the
internal shift register logic. The unselected bits of TB are ignored, and the unselected bits
of RB will not be valid and should be ignored by the receiver service routine.
The Clock Control
allows the adaptation of transmit and receive behavior of the SSC to
a variety of serial interfaces. A specific clock edge (rising or falling) is used to shift out
transmit data, while the other clock edge is used to latch in receive data. Bit CON.PH
