TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges
User’s Manual
6-25
V2.0, 2007-07
Buses, V2.0
6.5.1.3
Starvation Prevention
Starvation prevention is a feature that is especially important for the SPB. Because the
priority assignment of the SPB agents is fixed, it is possible that a lower-priority bus
requestor may never be granted the bus if a higher-priority bus requestor continuously
asks for, and receives, bus ownership. To protect against bus starvation of lower-priority
masters, an optional feature of the TC1796 will detect such cases and momentarily raise
the priority of the lower-priority requestor to the highest priority (above all other priorities),
thereby guaranteeing it access.
Starvation protection employs a counter that is incremented each time an arbitration is
performed in the BCU. When this counter reaches a user-programmable threshold
value, for each active bus request a request flag is stored in the BCU. This flag is cleared
automatically when a master is granted the bus.
When the counter reaches the threshold value, it is automatically reset to zero and starts
counting up again. When the next period is finished, an active request of a master from
which the request flag was set, a starvation event happened. This master will now be set
to the highest priority and will be granted service. If there are several masters to which
this starvation condition applies, they are served in the order of their hard-wired priority
ranking.
Starvation protection can be enabled and disabled through bit SBCU_CON.SPE. The
sample period of the counter is programmed through bit field SBCU_CON.SPC. SPC
should be set to a value at least greater than or equal to the number of masters. Its reset
value is 40
H
.
Note: The RPB also provides the SPE starvation protection enable bit and the SPC
starvation protection counter bit field. Because of the RPB single master agent
configuration, RBCU_CON.SPE can be always disabled.
6.5.2
FPI Bus Error Handling
When an error occurs on a FPI Bus, its BCU captures and stores data about the
erroneous condition and generates a service request if enabled to do so. The error
conditions that force an error-capture are:
•
Error acknowledge: An FPI Bus slave responds with an error to a transaction.
•
Un-implemented address: No FPI Bus slave responds to a transaction request.
•
Time-out: A slave does not respond to a transaction request within a certain time
window. The number of bus clock cycles that can elapse until a bus time-out is
generated is defined by bit field xBCU_CON.TOUT.
When a transaction causes an error, the address and data phase signals of the
transaction causing the error are captured and stored in registers.
•
The Error Address Capture Register (xBCU_EADD) stores the 32-bit FPI Bus
address that has been captured during the erroneous FPI Bus transaction.
