Infineon Technologies TC1796, User Manual

Page: 203 / 2150

TC1796
System Units (Vol. 1 of 2)
Reset and Boot Operation
User’s Manual 4-11 V2.0, 2007-07
Reset, V2.0
Table 4-2 Effect of Reset on Device Functions
Module / Function Watchdog
Reset Software
Reset Hardware
Reset Power-On
Reset
Boot Configuration
taken from Bit field
HWCFG Bit fields
HWCFG or
SWCFG Bit field
HWCFG Bit field
HWCFG
CPU
SCU
1) 1) 1) 1)
BCUs, Bus System
Peripherals, PCP
(except System Timer)
System Timer
Optional
2)
Not affected
On-chip
Static RAMs DMI,
PMI Not affected,
reliable Not affected,
reliable Not affected,
reliable Affected,
unreliable
DMU,
PMU Not affected,
unreliable Not affected,
unreliable Not affected,
unreliable Affected,
unreliable
PCP
Memory Not affected
3)
Not affected
3)
Not affected
3)
Affected,
unreliable
On-Chip Caches
4)
Flash
Oscillator, PLL
Not affected Not affected Not affected
EBU
EBU Pins
Depending on Reset Configuration
Port Pins Tri-stated, weak pull-up active
5)
NMI Pin Not affected Disabled Disabled Disabled
Reset Out Pin HDRST Optional
OCDS L1 Debug
System Only if JTAG reset is also active
6)
1) For two of the SCU registers (PLL_CLC, RST_SR), the reset value depends on the reset source.
2) “Affected” or “not affected” depends on bit RST_REQ.RRSTM.
3) If only the PCP accesses its memory, the contents are reliable. If an access from the FPI Bus is performed
while the reset is activated, the content is unreliable.
4) The actual data contents of the cache are not affected through a reset; however, the cache tag information is
cleared, resulting in an “empty” cache.
5) While PORST is active it is guaranteed that the pins are in tri-state mode even if the core supply is not applied.
Therefore the external power supply should activate PORST if any power failure is detected.
6) Default JTAG reset state (open JTAG pins) is active. A connected debugger tool controls the JTAG reset.