TC1796
System Units (Vol. 1 of 2)
Data Memory Unit
User’s Manual
8-8
V2.0, 2007-07
DMU, V2.0
8.6
Program Local Memory Bus Interface (LMI)
The PLMB (LMI) interface is a unidirectional interface, allowing the DMI/DMU to do data
reads and writes into the PLMB-based modules such as e.g. Flash or EBU space.
Accepted DLMB-to-PLMB bus write transactions are never error acknowledged by the
LMI.
The data phase of a PLMB read transaction will be extended until the data is available.
The LMI will reject any legal transaction that it cannot handle at that particular time (e.g.
when the LMI is busy and a second LMI- related transaction request is requested). Other
DMU memory accesses can be performed in parallel.
LMI transactions may receive error acknowledgments to any transaction. In every case
the LMI responds to error acknowledgments by halting the ongoing transaction that
received the error acknowledge, and dropping this transaction from the LMI PLMB bus
master transaction queue. The PLMB bus is released completely (including LOCK) for a
single cycle before further transactions are processed.
8.6.1
Data Read Buffer
The LMI contains a data read buffer which makes it possible to cache one line of
16 bytes (= 128 bits) of data read from specific memory areas on PMU side.
Read Transactions
When the first read access to cachable memory areas is done, the LMI initiates a 2-beat
burst access on PLMB, requesting 128 bit of data. The start address for the burst is
generated by setting the last 4 bits of the address to 0.
Cachable memory regions for data accesses are:
Segment 8: 8000 0000
H
- 8FFF FFFF
H
In all other memory regions mapped via the LMI, normal non-burst accesses of the
requested data size are initiated and the read data are not stored in the read buffer. The
read data cache buffer content remains unmodified.
For subsequent accesses into cachable memory regions, it is checked, whether the data
is completely contained in the buffer:
•
If this is true, the data is extracted out of the buffer without initiating an access to the
PLMB.
•
If the data is not contained in the buffer, a new 2-beat burst access is performed to
the PLMB as previously described, and the read data is stored in the buffer.
The requested data can only be extracted after all 128 bits have been read; thus a
cached access will take 1 cycle longer than non-cached access. As the cachable
memory regions are also visible in non-cachable areas (see address map), the user can
map the data dependent on his application to optimize between additional latency and
