TC1796
System Units (Vol. 1 of 2)
LMB External Bus Unit
User’s Manual
13-50
V2.0, 2007-07
EBU, V2.0
13.8
Asynchronous Read/Write Accesses
Asynchronous read/write access of the EBU support the following features:
•
LMBCLK clock-synchronous signal generation
•
Support for 16-bit and 32-bit bus width
Performing an PLMB access with a data width greater than that of the external device
automatically triggers a sequence of the appropriate number of external accesses to
match the PLMB access width.
•
Demultiplexed address/data lines
•
Programmable access parameters
– Internal control of command delay cycles
– External and/or internal control of wait states
– Variable data hold cycles for write operation (to allow flexible hold time adjustment)
– Variable inactive/recovery cycles when:
Switching between different memory regions (CS),
Switching between read and write operations,
After each read cycle,
After each write cycle.
Software driver routines are required in order to support Nand Flash devices using
asynchronous device accesses. A single Nand Flash access sequence is performed by
generating the appropriate sequence of discrete asynchronous device accesses in
software.
The EBU does not provide support 8-bit bus width. When 8-bit SRAM devices are used,
they must be used in pairs to implement either a 16-bit or 32-bit wide memory region.
13.8.1
Signal List
The following signals of the EBU are used for asynchronous accesses:
Table 13-16 Asynchronous Mode Signal List
Signal/Pin
Type
Function
D[31:0]
O
Data bus lines 0-31
A[23:0]
O
Address bus lines 0-23
CS[3:0]
O
Chip select 0-3
RD
O
Read control line
RD/WR
O
Write control line
MR/W
O
Motorola-style read/write control line
BC[3:0]
O
Byte control lines 0-3
WAIT
I
Wait input
