TC1796
System Units (Vol. 1 of 2)
Reset and Boot Operation
User’s Manual
4-7
V2.0, 2007-07
Reset, V2.0
4.2
Reset Operations
4.2.1
Power-On Reset
The PORST pin performs a power-on reset, also called cold reset. Driving the PORST
pin low causes an asynchronous reset of the entire device. The device then enters its
power-on reset sequence.
The PLL has its own power-on reset circuitry and is not affected by any other reset
condition besides a low signal transition on the PORST pin. With an active power-on
reset, the PLL is disconnected from the oscillator and will start running at its base
frequency.
Simultaneously with PORST low, the reset circuitry drives the HDRST pin low and waits
for the following two conditions to occur:
1. The system clock is active
2. Pin PORST is put to inactive level (driven high)
When both of these conditions are met and HDRST is not further pulled low externally,
the power-on reset sequence is terminated synchronously with the next system clock
transition.
The rising edge of PORST causes the state of some of the configuration pins for the PLL
and the boot options to be latched into the appropriate registers. Others are latched with
the rising edge of HDRST. Fields in the Reset Status Register (RST_SR) are set to
inform the user about this complete reset of the device. The power-on reset indication
flag is set, while all other reset cause indication flags are cleared. Fields in this register
which are set include the power-on reset indication flag (PWORST), as well as the reset
status flags for the System Timer (RSSTM) and the reset output pin state (RSEXT).
The time PORST has to be active after the supply voltage is stable depends mainly on
the settling time of the power supply lines. It does not directly depend on the oscillator
start up time because a system clock signal will be provided already by the PLL in PLL
Base Mode as soon as the power supply lines are stable. This system clock signal is a
slow clock signal based on the VCO base frequency. More details on the PLL Base Mode
are discussed on
.
PORST is equipped with a noise-suppression filter that suppresses glitches below 10 ns
pulse width. PORST pulses with a width above 100 ns are safely recognized as a valid
signal. The noise-suppression filter is switched-off when pin BYPASS = 1.
4.2.2
External Hardware Reset
The external hardware reset pin HDRST serves as an external reset input as well as a
reset output. It is an active-low, bi-directional open-drain pin with an internal weak pull-
up. An active-low signal at this pin causes the chip to enter its hardware reset sequence.
