TC1796
Peripheral Units (Vol. 2 of 2)
General Purpose Timer Array (GPTA)
User’s Manual
24-67
V2.0, 2007-07
GPTA, V2.0
24.2.3.3 Local Timer Cell (LTC00 to LTC62)
LTC00 to LTC62 are functionally identical. The functionality of LTC63 is different to
LTC00 to LTC62 and therefore described separately at
Registers
The following registers are assigned to a Local Timer Cell LTCk (k = 00-62):
•
LTCCTRk = Local Timer Cell Control Register k (see
•
LTCXRk = Local Timer Cell X Register k (see
•
SRSC2 = Service Request State Clear Register 2 (see
•
SRSC3 = Service Request State Clear Register 3 (see
•
SRSS2 = Service Request State Set Register 2 (see
)
•
SRSS3 = Service Request State Set Register 3 (see
)
Features
•
16-bit based timer cells
providing capture, compare, and timer functions.
•
Capture Mode
on rising, falling or both edges with following actions:
– Service request generation
– Output signal transition generation (set, reset, toggle the output signal).
•
Compare Mode
on equal compare of the corresponding (Reset-)Timer LTC with
following actions:
– Service request generation
– Output signal transition generation (set, reset, toggle the output signal).
•
Timer Mode
incremented on hardware signal with following actions:
– Event generation at overflow
– Service request generation
– Output signal transition generation (set, reset, toggle the output signal).
•
Reset Timer Mode
allows the selected LTC to be reset by an adjacent cell. Coherent
update capability of adjacent LTCs for PWM management is provided.
•
One Shot Mode
allows the selected (capture, compare, timer or reset timer) mode
to be stopped after the first event.
•
Flexible mechanism
to link pin actions and allow complex combination of cells. (A
cell has the ability to propagate actions over adjacent cells with higher number, in
order to perform complex waveforms such as multi channel PWMs).
Architecture
The architecture of an LTC is shown in
. Each LTC has a 16-bit
capture/compare register and a 16-bit equal to comparator.
